The present invention relates to interface circuits and more particularly, to an interface circuit having a receiving side circuit which can control logical threshold values such that the logical threshold values can comply with a received signal even when it varies changes in either a direction toward the supply potential or a direction toward the ground potential, in a system in which a voltage variation occurs in a transmitting signal by reason that a supply voltage power source provided on the sending side differs from that provided on the receiving side or in a signal transmitting system in which noise is contained in a transmitting signal by reason that supply voltage varies.
As a conventional transmission system of this type, a system has been known in which an interface circuit is adapted for the case where different power source systems are provided on the sending and receiving sides in a signal transmission system or for the case where a variation in supply voltage causes a transmitting signal to vary in voltage level and, when a transmitting data signal of opposite polarities in the form of non-inverting and inverting signals is delivered from the sending side, a voltage difference between the received opposite-polarity signals is extracted to decide logic of the transmitting signal on the receiving side.
An example of this type of interface circuit is described in JP-A-2-185110. An interface circuit described in this literature is constructed of an emitter coupled logic (ECL) circuit and has means for obtaining, as a discrimination voltage, a middle voltage between high and low logical levels from a clock signal contained in an input signal supplied from a transmitting system, and means for comparing the obtained discrimination voltage with an input signal level to decide the level of the input signal, thereby making it possible to suppress a decrease in operating margin or a variation in duty which results from a voltage variation caused by, for example, a transmission loss.
Another example is described in JP-A-62-180643. An interface circuit described in this literature uses a ground potential difference between the sending and receiving sides to prevent a change in delay time and a decrease in noise margin and is constructed of an ECL circuit similarly to the aforementioned interface circuit. More specifically, a reference potential Vref for formation of a pulse signal to be transmitted is provided an only the sending side, and the receiving side utilizes the reference potential Vref on the transmitting side to match a reference of comparison potential to the reference on the sending side so that the influence of a difference in ground potential on the delay time may be neglected and signal transmission of wide noise margin may be effected.
On the other hand, an example of an interface circuit adapted for the case where noise is contained in a transmitting signal is described in JP-A-7-193471. This is a semiconductor waveform converting circuit and uses, in a receiver circuit on the receiving side, a Schmitt circuit having such a hysteresis characteristic that the logical threshold value is set to be high corresponding to rise of an input signal and low corresponding to fall of the input signal, thus filling the role of eliminating noise in the transmitting signal. The logical threshold value referred to herein indicates an input signal voltage value which provides an output signal 1of an output signal voltage value equal to 1/2 of the logical amplitude in an inverter circuit, a buffer circuit, a receiver circuit or a waveform converting circuit.
JP-A-8-18432 discloses an example of an inverter circuit adapted for the case where a transmitting signal obtained on the receiving side becomes a signal exhibiting a gradual change characteristic owing to a long transmission line and a load of large capacity and a large delay time occurs. A receiver circuit uses a circuit in which the logical threshold value is set to be low corresponding to rise of a transmitted input signal and to be high corresponding to fall of the input signal to exhibit a characteristic inverse to the hysteresis characteristic.
The aforementioned conventional interface circuits will be detailed with reference to FIG. 8 schematically showing the construction of an example of conventional interface circuit, FIG. 9A schematically showing the construction of another example of conventional interface circuit and FIG. 9B showing operational characteristics on the sending or transmitting and receiving sides. The interface circuit of FIG. 8 uses as a driver circuit a waveform converter 7 which receives an input signal of a transmitting signal N21 to deliver transmitting signals of opposite polarity signals in the form of non-inverting and inverting signals N22 and N23 of the input signal and uses as a receiver circuit a waveform converter 8 which determines logic of the transmitting signal from a potential difference between the received transmitting signals N22 and N23 to deliver an output signal N24.
In the interface circuit as above, when supply voltage on the transmitting side varies or a transmission loss occurs in the signal transmission line, the transmitting signals N22 and N23 are equally affected by the variation or the loss and in consequence, the potential level relation between the transmitting signals N22 and N23 remains unchanged and the logic can be recognized accurately from the potential difference between the transmitting signals N22 and N23 on the receiving side.
The different conventional interface circuit shown in FIG. 9A has as a driver circuit a waveform converter 9 for comparing a reference potential Vref and an input signal to be transmitted and determining logic of the input signal from the difference and has as a receiver circuit a waveform converter 10. Namely, a reference potential Vref is generated by the driver circuit 9 on the transmitting side and the reference potential Vref is used in the receiver circuit 10, too.
For example, given that the transmitting signal N26 delivered out of the transmitting side driver circuit 9 has a minimum value of high level which is VOH and a maximum value of low level which is VOL, a minimum value for the receiving side receiver circuit 10 to recognize the input signal as high level is VIH and a maximum value for the receiving side receiver circuit 10 to recognize the input signal as low level is VIL, a noise margin NMH for high level is defined by "VOH-VIH" and a noise margin NML for low level is defined by "-(VOL-VIL)".
The transmitting signal N26 and the reference potential Vref are equally affected by a supply voltage variation on the transmitting side and a transmission loss in the signal transmission path. Accordingly, when voltage variations occur in the transmitting signal and the reference potential and the VOH, VOL and Vref shift from threshold value levels N29 to threshold value levels N30 as shown in FIG. 9B, the VIH and VIL shift similarly because the reference potential on the transmitting side equals the reference potential Vref on the transmitting side and noise margins NMH and NML remain unchanged.
When the reference potential of the waveform converter is generated on the transmitting side by itself, the VIH and VIL do not shift to VIH' and VIL' and so the noise margins NMH and NML shift to NMH' and NML', with the result that a characteristic against noise is degraded. In other words, as compared to the case where the reference potential on the receiving side is generated by the waveform converter 10 by itself, the interface circuit can advantageously increase the margin for noise due to the supply voltage variation on the transmitting side and the transmission loss.
Referring to FIG. 10 showing a receiver circuit 22 of an interface circuit for performing transmission of a plurality of signals, the receiver circuit 22 has waveform converters 221, 222 and 223 and decides logic of an input signal from a potential difference between a reference potential and the input signal.
In the receiver circuit, one 221 of the waveform converters 221 receives a clock signal as an input transmitting signal. On the output side, there is provided a reference potential generating circuit 224 for obtaining, as a reference potential of the receiving side waveform converter 22, a middle potential Vref between high and low levels of another transmitting signal from the transmitted clock signal N28. A supply voltage variation on the transmitting side and a transmission loss in the signal transmission path take place in the form of potential changes in high and low levels of the transmitting signal N28.
By using the middle potential between high and low levels as the reference potential of the receiving side waveform converter 22, a voltage variation equal to a voltage variation in the transmitting signal can be taken into the reference potential on the receiving side. Accordingly, as compared to the case where the reference potential of the receiving side waveform converter is generated on the receiving side by itself, the noise margin can be advantageously increased.
Referring to FIG. 11A showing a circuit diagram of an example in which a receiver circuit having a high noise margin is constructed of MOS transistors, FIG. 11B showing an operational characteristic of the receiver circuit and FIG. 11C showing a conceptive diagram for explaining the noise margin, the receiver circuit, designated by reference numeral 23, has P-channel type MOS transistors 231a and 232 and N-channel type MOS transistors 233 and 234a which are connected in series between supply potential and ground potential GND, gate electrodes of these transistors being connected in common to receive an input signal N29, a P-channel type MOS transistor 231b connected in parallel with the P-channel type MOS transistor 231a, and an N-channel type MOS transistor 234b connected in parallel with the N-channel type MOS transistor 234a. The P-channel type MOS transistor 232 has its drain electrode connected to gate electrodes of the P-channel type MOS transistor 231b and N-channel type MOS transistor 234b through an inverter 235, and an output signal N30 is delivered lout of the inverter 235.
In this receiver circuit 23, since the transistors 231b and 234b contribute to logical threshold values of this circuit in such a manner that the output signal N30 is not liable to be inverted in response to a change in the input signal N29, the output signal will not be inverted before the input signal N29 sufficiently changes toward a high level or a low level.
This type of waveform converter exhibits a high logical threshold value VTHR in response to rise of the input signal and a low threshold value VTHF in response to fall of the input signal and therefore it is a Schmitt circuit having a hysteresis characteristic.
In such a Schmitt circuit, the input signal is not recognized before the input signal reaches VIL or VIH. In this case, noise margins are indicated by NMH=(VOH-VIL) and NML=-(VOL-VIH) and accordingly, the Schmitt circuit can provide large noise margins.
By using the waveform converter having the large noise margins in the receiver circuit, noise in the transmitting signal can be removed.
Referring now to FIG. 12A showing a circuit diagram of an example of a receiver circuit in which the transmission delay time is decreased and FIG. 12B showing an input/output characteristic of the circuit, the receiver circuit is constructed of two of the receiver circuits 23 of FIG. 11A used in combination.
More particularly, the receiver circuit of FIG. 12A differs from the receiver circuit 23 of FIG. 11A in that transistors 241b and 244b of one waveform converter have their gate electrodes connected to a drain electrode of a transistor 247 of the other waveform converter and that an output signal N32 is delivered out of an inverter 245 of the one waveform converter.
In this receiver circuit, a circuit having transistors 246a, 247, 248, 249a and 249b forms a Schmitt circuit and the transistors 241b and 244b contribute to logical threshold values in such a manner that the output of the receiver circuit is liable to be inverted in response to a change in an input signal N31. Accordingly, a slight change of the input signal causes the output signal to change.
Namely, the waveform converter as above operates such that it exhibits a low logical threshold value VTHR in response to rise of the input signal and a high logical threshold value VTHF in response to fall of the input signal.
As shown in FIG. 12B, this circuit has an input/output characteristic inverse to that of the aforementioned Schmitt circuit by exhibiting VTHF which is higher than VTHR. When a transmitting signal on the receiving side changes gradually owing to a long transmission line and a load of large capacity and a delay time due to the long transmission line, a change in the transmitting signal can be sensed earlier and the delay time can be reduced by using the receiver circuit as above.
As described above, in the conventional interface circuit of FIG. 8, two transmitting signals of non-inverting and inverting signals are needed for one transmitting signal and in consequence, the number of signal wiring lines for interface increases.
In the conventional interface circuit of FIG. 9A, at least one signal wiring line is needed for transmission of the reference potential in addition to the signal wiring line for the transmitting signal and when bidirectional communication is taken into consideration, at least two signal wiring lines for bidirectional transmission of the reference potential are needed in addition to the signal wiring line for the transmitting signal.
On the other hand, in the interface circuit of FIG. 10, no signal wiring line is needed for transmission of the reference potential but the clock signal must be transmitted necessarily to the receiving side and therefore, when no clock signal is contained in the transmitting signal, a signal wiring line for transmission of the clock signal must be added.
On the other hand, in the receiver circuits 23 and 24 shown in FIGS. 11A and 12A, an optimum margin can be provided by changing VIM and VIL on the receiving side in response to a voltage variation in the transmitting signal but the width of the VIH and VIL cannot be changed, with the result that as the width of VOH and VOL of the transmitting signal is narrowed, the noise margin is also decreased.
Especially, when VOM.ltoreq.VIM or VOL.gtoreq.VIL, NMH.ltoreq.0 or NML.ltoreq.0 holds and transmission of accurate logic is prevented.
The receiver circuit 23 can afford to have a large noise margin but has a characteristic which is sensitive to a voltage variation in the transmitting signal when the noise margin is increased. More specifically, in the Schmitt circuit, increasing the noise margin means that VIH approaches VOM and VIL approaches VOL and when a voltage variation causes VOM &lt;VIM or VOL&gt;VIL to stand, the noise margin becomes "0" to raise sensitivity to noise.
The receiver circuit 24 decreases the noise margins NMH and NML to permit a change in the transmitting signal to be sensed earlier but because of the small noise margins, its characteristic is sensitive to a voltage variation in the transmitting signal. Namely, when VOM.ltoreq.VIM or VOL.gtoreq.VIL holds, NMH.ltoreq.0 or NML.ltoreq.0 stands and the receiver cannot recognize logic accurately.
As described above, the conventional interface circuits cannot maintain the noise margin when voltage in the transmitting signal changes and cannot recognize the fact that transmission of accurate logic is prevented owing to the failure to maintain the noise margin.